7.3.2 Performance Features For enhanced performance, the BIOS sets up the L2 cache controller for the Pentium ® III processor and performs option ROM shadowing. 7.3.2.1 L2 cache Initialization To boost system performance, the processor contains an L2 cache and cache controller, which previously had been handled by external devices. The BIOS programs the processor’s L2 cache controller in a manner that is consistent with the chipset. The L2 cache is tested as a part of the processor BIST. The BIOS detects the cache size and cache type (ECC or non - ECC), and programs the cache controller accordingly before performing any cache operations. Table 48 describes the default values loaded i n the MTR registers. 0292名無し~3.EXE2022/05/14(土) 18:36:54.75ID:d1Q49gdh Overview The SRMK2 serverboard features are summarized in Table 14 . Table 14 : SRMK2 featu re summary Form Factor Serverboard dimension: 10.4” x 11.3” Processor Supports Dual Pentium ® III processors using PGA370 sockets Memory • Four 168 - pin dual inline memory module (DIMM) sockets • Supports only registered SDRAM DIMMs • Supports up to 4 GB of E CC, SPD Registered SDRAM DIMMs Chipset ServerWorks® ServerSet™III LE Chipset, consists of: • ServerWorks CNB30LE North Bridge Front Side Bus Interface chip • ServerWorks OSB4 South Bridge chip 0293名無し~3.EXE2022/05/14(土) 18:51:57.18ID:d1Q49gdh MTRR registers:
